The on-going demand for high performance electronic systems has driven the need for high-speed digital Very Large Scale Integration (VLSI) chips. VLSI implementations have proceeded in two inter-related directions: higher performance and higher density (more devices per unit area). While modern VLSI chips have achieved astonishingly high levels of performance and chip density there is a very strong demand for even higher levels.
One serious impediment to achieving what is demanded from VLSI devices is power consumption. As a rule of thumb higher performance requires more power. But, more power produces more heat, which increases failure rates. Consequently, power consumption is the predominant challenge in improving modern high performance systems.
Almost all modern VLSI chips are clocked. That is, the operations of the gates within a VLSI chip are synchronized to act together by clock signals. So long as the gates can keep up, the higher the clock rate the faster the performance. Unfortunately, as clock rates and VLSI chip densities increase it becomes very difficult to ensure that all of the chips can keep up with the clocks. One reason for this is that each sequential element in a VLSI chip needs its own clock signal, but not all devices are the same distance from the clock signal source, which means that all clock lines are not the same length and that associated parameters such as distributed capacitances and resistances, differ. Different lengths coupled with unavoidable signal delays caused by distributed resistances and capacitances mean that clock signals arrive at different devices at different times (clock skew). Such can effectively limit the performance of a VLSI chip.
Compounding the clocking problems is the fact that clocking requires power. In fact, the on-chip clock distribution network (CDN) of modern VLSI chips often consumes more than 35% of the total chip power and can occasionally require as much as 70%.
Various approaches have been attempted in the prior art to address VLSI clocking problems. One approach to decreasing CDN power consumption is to use resonant clocks in the VLSI clock distribution network. FIG. 1 illustrates an LC tank resonant clock 10.
Ideally, by oscillating clock energy between the electric field of capacitance Cs 12 and the magnetic field of inductor Ls 14 the clock energy is recycled and power consumption is decreased (ideally to zero). The resonant frequency of the tank (Cs 12 and Ls 14) without parasitic Cd 16, Rwr 18 and Rw1 20 is ideally:f−½π√{square root over (LsCs)}
However, to provide the required CMOS logic levels of zero and Vdd 8 a positive bias is obtained by adding a decoupling capacitor Cd 16 on the grounded end of the paralleled inductor Ls 14, as shown in FIG. 1. That additional capacitance Cd 16 creates a parasitic series LC tank circuit. Careful sizing of Cd 16 must be taken to ensure that the series resonant frequency is well separated from the parallel resonant frequency, i.e.:½π√{square root over (LsCd)}<<½π√{square root over (LsCs)}
In practice, pure series/parallel LC tanks are not seen because of unavoidable wire resistances, specifically: Rw1 20, the conductor resistance between the clock driver and the inductor, Rwr 18, the conductor resistance between the inductor and the clock capacitor Cs 12, the driving element resistance Rdr, 22 and the parasitic resistance of the inductor Rs 24.
Those unavoidable wire resistances shift the resonance frequency of the LC tank resonant clock 10 downward and change that oscillator's Q. Furthermore, the placement of an LC tank in the clock distribution determines the attenuation. Consequently, where the LC tanks are placed in a clock distribution network is of utmost concern.
On-chip inductors can be created using normal metal layers, special layers in RF processes, or using free-standing MEMs devices. But, the on-chip inductors 26 using square spiral topologies with ground shields as shown in FIG. 2 are common and useful. It will be assumed herein that the inductance of such on-chip inductors 26 is:
  L  -      0.0002    ⁢                  ⁢          l      〚                        ln          ⁢                                    2              ⁢                                                          ⁢              l                                      w              +              t                                      +        0.5        +                              w            +            t                                3            ⁢                                                  ⁢            l                              〛        ⁢    nH  
where n is the number of turns, w is the width of a trace, t is the thickness of the metal, l is the length of trace and S is the spacing between turns. Given n, s, w, di (inner diameter of the square spiral inductor), do (outer diameter of the square spiral inductor) the chip areas occupied by an on-chip inductor 26 isArea=d02=(di+2n(s+w))2 
While very promising in theory, VSLI resonant clock networks are seldom used, usually being restricted to VLSI clock distribution networks that use H-trees. Referring now to FIG. 3a, an H-tree 30 is a conductor topology for minimizing clock skew by making interconnections to VLSI circuit “subunits” equal in length by using a regular pattern of clock line conductors 32. An H-tree 30 is a symmetric tree topology and has been used with drive clock grids having driver buffers in the top-level tree. Clock grids are formed by a set of vertical and horizontal wires with stubs connecting clock sinks. Refer to FIG. 3b for a depiction of a resonant H-tree and grid 36 augmented by distributed LC tanks placed at H-trees. While an H-tree can have many different levels, in the prior art the LC tanks 35 were always placed at the input of the second level in a 2-level H-tree network as shown in FIG. 3a. 
While conceptually interesting, VLSI resonant clock distribution networks are seldom if ever used. A major problem is that prior art resonant clock distribution networks required even (balanced) distribution of gates, terminals, loads, distributed capacitance and inductances and conductors. Uneven loading of resonant clock distribution networks significantly alters resonant behavior and can prevent correct functionality of LC tanks. As LC tanks can only be placed in the H-tree 30, and one LC tank only resonates with one clock sector (as shown in FIG. 3a) which result in a large amount of on-chip inductors. Such limitations are neither practical nor realistic in actual VLSI designs.
Instead of placing LC tanks in the H-tree, LC tanks 50 can be connected directly to the clock grid 52 to save power more efficiently as shown in FIG. 4. However, resonant clock grids present several unique challenges to automated designs compared to fully buffered grids. First, the parasitic resistances and inductances in a clock distribution alter the resonant frequency. Second, the resistances add attenuation at high frequencies. Third, the unsymmetrical structure of clock network and unbalanced load require precious inductor sizing. Fourth, the shared output node in a resonant grid causes interactions between the buffers and the LC tanks 50. Such factors all lead to altered resonant frequencies and phase conflicts. No successful prior art method to address those problems has been implemented.
Implementing VSLI resonant clock grids requires implementing the clock grid 52 conductors and then obtaining the correct LC placement and sizing. When clock distribution networks incorporate resonant tanks the LC tanks 50 are inserted at points in the clock grid 52 so as to resonate each subunit clock sector.
Therefore, a technique that minimizes clock skew and power with minimum inductor area overhead by implementing LC tank 50 placement, sizing and driver buffer sizing would be beneficial. Ideally, the technique would be suitable for automatic implementation at the design level.